Interpretation of T/CASAS 033-2024: Switching Dynamic Test Method for Silicon Carbide MOSFET Power Devices

1.1 Background of Standard Development

For a long time, the industry lacked a quantitative technical specification and standardized test method for SiC MOSFET switching dynamics. Test results from different manufacturers and laboratories were difficult to trace and compare with each other, and this inconsistency became a major bottleneck for the development of the third-generation semiconductor industry.

1.2 Significance of the Standard

• At the technical level: it establishes a scientific, unified, and operable test methodology for characterizing SiC switching behavior.
• At the industrial level: it solves the long-standing problem of incomparable and non-traceable test results.
• At the innovation level: it promotes upgrades in test instruments and equipment.
• At the international level: it supports China's participation in international standardization for third-generation semiconductors.

2.1 Scope of Application

• Discrete-package SiC MOSFET devices.
• Module-package SiC MOSFET devices.
• SiC MOSFET products across voltage classes such as 650V, 1200V, and 1700V.
• Coverage of principles, circuit requirements, instrumentation, test conditions, measurement methods, and safety requirements.

2.2 Drafting Organizations

The standard was led by Chongqing University and jointly drafted by 28 organizations including CR Micro Runan, Huafeng Test & Control, Keysight, Tektronix, Chenxin Technology, and CRRC Times Semiconductor. The participating organizations span universities, device manufacturers, test equipment vendors, and application enterprises, reflecting a strong industry-academia-research-user collaboration model.

3.2 Method Advantages

• Low thermal impact: the very short test duration minimizes junction temperature drift.
• Comprehensive parameters: turn-on, turn-off, and reverse recovery characteristics can be obtained in one test framework.
• High realism: the method reflects practical device operating conditions.
• High repeatability: test conditions are controllable and results are reproducible and traceable.

3.3 Test Circuit Design Essentials

• A DC power supply provides stable test voltage.
• The DC bus capacitor supplies transient high current and stabilizes the bus voltage.
• The clamp inductor serves as the load inductance and provides a continuous current path.
• The driver circuit provides gate drive, while the freewheeling device provides the freewheeling path.

3.4 Control of Parasitic Power-Loop Inductance

• Because SiC devices switch extremely fast, parasitic loop inductance can generate significant voltage overshoot.
• The standard requires this inductance to be minimized and explicitly reported in test results.
• Laminated busbars and compact layouts are recommended.

3.5 Clamp Inductor Design

• An air-core inductor should be used to avoid inductance variation caused by core saturation.
• The inductance value must remain stable at the maximum test current.
• The equivalent parallel capacitance CEPC should not exceed 10% of the DUT output capacitance.

4.1 Environmental Conditions

• Ambient temperature: 25°C ± 5°C.
• Relative humidity: 45% to 75%.
• Atmospheric pressure: 86kPa to 106kPa.
• If the environment is outside the standard range, the deviation should be stated in the report.

4.2 DC Power Supply Requirements

• The supply should provide adjustable DC output from 0 to the rated voltage.
• Current output capability should meet the test demand.
• Output ripple should be sufficiently low.
• Voltage stability must be maintained throughout testing.

5.1 Oscilloscope Requirements

• Bandwidth should be at least 500MHz, matching the voltage probe.
• Vertical resolution should be at least 10 bits.
• Noise should be below 1mVrms at 1V/div and 50Ω input impedance.
• At least four channels are recommended, with inter-channel timing mismatch below 0.5ns.

5.2 Sampling Rate Considerations

Although the standard does not explicitly specify sampling rate, it should be at least twice the highest signal frequency. For 500MHz bandwidth signals, 2.5GSa/s is the minimum practical recommendation, while 5GSa/s or more is preferred for reliable waveform reconstruction and parameter extraction.

6.1 Definitions of Switching Time Parameters

• Turn-on delay time td(on): the interval from the gate voltage reaching 10% of its steady-state value to the drain current reaching 10% of its steady-state value.
• Rise time tr: the interval for drain current to rise from 10% to 90% of its steady-state value.
• Turn-off delay time td(off): the interval from the gate voltage falling to 90% of its steady-state value to the drain current falling to 90% of its steady-state value.
• Fall time tf: the interval for drain current to fall from 90% to 10% of its steady-state value.

6.2 Calculation of Switching Losses

• Eon: integrate Vds(t) × Id(t) from the instant the gate voltage rises to 10% of steady-state until Vds falls to 3% of steady-state.
• Eoff: integrate Vds(t) × Id(t) from the instant the gate voltage falls to 90% of steady-state until drain current falls to 3% of steady-state.
• Err: integrate Vsd(t) × Isd(t) from the start of source-drain voltage decay until source-drain current falls to 2% of peak value.

7.1 Electrical Safety

• The test system must be reliably grounded and meet relevant grounding resistance requirements.
• High-voltage sections should be isolated by protective barriers.
• After testing, the DC bus capacitor must be discharged to a safe voltage before handling the DUT.

7.2 Operating Discipline

• Testing should be carried out by two or more trained professionals.
• Operators should wear insulating gloves, safety goggles, and other personal protective equipment.
• Emergency procedures and first-aid equipment should be prepared.

7.3 High-Temperature Safety

• High-temperature areas should be clearly marked with warning signs.
• The thermal platform should cool down to a safe temperature before handling.
• Special tools should be used when touching hot parts.

8.1 Referenced Standards

• GB 4793.5-2008: Safety requirements for probe assemblies.
• GB/T 15289-2013: General specification for digital storage oscilloscopes.
• T/CASAS 002-2021: Terminology for wide-bandgap semiconductors.
• T/CASAS 006-2020: General specification for SiC MOSFETs.
• JEP 190-2022: Guideline for evaluating the dv/dt robustness of SiC power devices.

8.2 Comparison with International Standards

• IEC does not yet have a dedicated standalone standard specifically for SiC MOSFET switching dynamic testing.
• This standard raises bandwidth expectations for test instruments compared with more general methods.
• It explicitly defines high-speed switching test methodology and adds thermal test requirements.
• Compared with JEDEC documents, it provides more detailed test-circuit, measurement, and safety guidance.

9.1 Advancing Industrial Standardization

• It unifies the technical method for SiC MOSFET switching dynamic testing.
• It standardizes the full workflow from setup to result processing.
• It provides a common benchmark for device design and optimization.

9.2 Improving Result Comparability

• It makes results traceable by clarifying test conditions and measurement rules.
• It allows results from different manufacturers and laboratories to be compared on the same basis.
• It improves the credibility of test data for end users and supply chains.

9.3 Supporting Localization and Capability Building

• It provides a technical foundation for domestic test equipment development.
• It supports performance evaluation and quality control of domestic SiC devices.
• It helps cultivate specialized test engineering talent.